CMOS has been the basic logic building block in the digital-dominant world for decades. Device dimensions have been continuously reduced in order to achieve higher performance as well as packing density. Gate depletion effects arising from the finite dopant activation in the poly gate have become more and more significant as gate dielectric thickness is scaled below 20 Å. Gate depletion effects induce a voltage drop across the gate depletion region and result in greater effective oxide thickness (EOT) as well as lower current drive. On the other hand, device scaling also necessitates ultra-shallow source/drain extensions with high conductivity in order to simultaneously suppress short-channel effects and source/drain series resistance. However, the targets for source/drain extension in sub-65 nm technologies have become less likely to be met utilizing conventional implant and anneal techniques.
Metal gates have been demonstrated to completely eliminate gate depletion effects and improve device performance. In such an approach, a dual metal scheme in which different metals are used for nMOS devices and pMOS devices is required in order to achieve symmetric and low threshold voltage (Vth) for both nMOS and pMOS devices. It has been shown that, for ultra-thin body silicon on insulator transistors (SOI) or Fin field effect transistors (FinFET) where Vth adjustment is no longer controlled by channel implant, a work function less than about 4.5 eV for nMOS and greater than about 4.9 eV for pMOS must be adopted. However, the process of selective dual metal stacks suffers complicated integration issues such as difficult dual-metal etch requirements, low thermal tolerance, etc. J. Kedzierski, et al. demonstrated a simpler dual-metal gate process on FinFETs, employing total gate silicidation and source/drain silicidation at once. The article is incorporated herein by reference. Various implants prior to gate silicidation are adopted to achieve gate work function in the range of 4.3 eV and 4.8 eV. However, this simple approach is incompatible with bulk technology because the use of a thin dummy poly gate for total gate silicidation is likely to be implanted through during the deep source/drain implantation which is needed for reducing junction leakage and series resistance.
In the quest for ultra-shallow and highly conductive source/drain extension, S. Rishton et al. have demonstrated the feasibility of metal source/drain extensions with differential metal silicide source/drains for nMOS and pMOS, respectively. However, the finite barrier height between the source and channel often presents a strong series resistance effect. Therefore, a low Schottky barrier is necessary for high drive current. ErSi and PtSi have been demonstrated to be best suited for nMOS and pMOS Schottky source/drain regions, respectively, so that a barrier height less than 0.3 eV can be achieved. However, for higher performance, a barrier height less than about 0.2 eV and therefore a metal work function of less than 4.3 eV for nMOS and greater than about 4.9 eV for pMOS is preferred. Hence, novel techniques for work function tuning (other than careful selection of metal materials) are of great importance for optimization of Schottky source/drain region technology.